gennum corporation p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 e-mail: info@gennum.com www.gennum.com revision date: may 2005 document no. 14583 - 04 data sheet gs7032 features ? smpte 259m-c compliant (270mb/s) serializes 8-bit or 10-bit data minimal external components (no loop filter components required) isolated, dual-output, adjustable cable driver 3.3v and 5.0v cmos/ttl compatible inputs lock detect indication smpte scramble and nrzi coding bypass option edh support with gs9001, gs9021 pb-free and rohs compliant application smpte 259m-c parallel to se rial interfaces for video cameras, vtrs, signal generators; generic parallel to serial conversion. description the gs7032 is designed to encode and serialize smpte 125m bit parallel digital video signals as well as other 8-bit or 10-bit parallel formats. this device performs the following functions: ? sync detection parallel to serial conversion data scrambling (using the x 9 + x 4 + 1 algorithm) 10x parallel clock multiplication conversion of nrz to nrzi serial data the gs7032 features 270m/bs da ta rate with a single vco resistor. other features includ e a lock detect output, nrzi encoding and smpte scrambler bypass, a sync detect disable, and an isolated dual output cable driver suitable for driving 75 ? loads. block diagram ordering information part number package temperature pb-free and rohs compliant gs7032 - cvm 44 pin tqfp 0c to 70c no gs7032 - cvme3 44 pin tqfp 0c to 70c yes lock detect (lock det) serial digital outputs parallel clock input (pclkin) p load s clk s clk /10 loop bandwidth control (lbwc) r vco+ r vco- mute reset reset sync detect disable (sync dis) bypass bypass parallel to serial converter & nrz to nrzi data in (pd0-pd9) 10 10 8 input latch 2 10 sync detect smpte scrambler pll sdo sdo prolinx ? gs7032 digital video serializer
14583 - 04 2 of 9 gs7032 absolute maximum ratings parameter value supply voltage (v s = v cc -v ee )5.5v input voltage range (any input) v ee 14583 - 04 3 of 9 gs7032 ac electrical characteristics v cc = 5v, v ee = 0v, t a = 0 ? 70c unless otherwise specified. parameter symbol conditions min typ max units notes test level serial data bit rate br sdo r vco = 374 ? - 270mb/s - mb/s smpte 259m-c 3 serial data outputs signal swing v sdo r load = 37.5 ? , r set = 54.9 ? 740 800 860 mvp-p 1 sd rise/fall times t r , t f 20% - 80% 400 - 700 ps 7 sd overshoot/undershoot - - 7 % 1 7 output return loss o rl at 270mhz 15 - - db 1 7 lock time t lock worst case - - 5 ms 6 min loop bandwidth bw min lbwc = grounded : bw min - 220 - khz 7 typical loop bandwidth bw typ lbwc = floating : bw min - 500 - khz 7 max loop bandwidth bw max lbwc = v cc : 10 bw min -1.7-mhz 7 intrinsic jitter (6 )lbwc = v cc (270mb/s) - 0.08 - ui 3 data & clock inputs (pd[9:0] pclkin) t su setup time at 25c 2.5 - - ns 3 t h hold time at 25c 2.0 - - ns 3 test levels 1. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. production test at room temperature and nominal supply voltage. 4. qa sample test. 5. calculated result based on level 1,2, or 3. 6. not tested. guaranteed by design simulations. 7. not tested. based on characterization of nominal parts. 8. not tested. based on existing design/c haracterization data of similar product. notes 1. depends on pcb layout. 10
14583 - 04 4 of 9 gs7032 pin connections gs7032 top view 44 43 42 41 40 39 38 37 36 35 34 r vco+ lf+ v ee r vco- lf- v cc1 lbwc nc sync dis v ee v ee1 33 32 31 30 29 28 27 26 25 24 23 nc bypass nc v ee nc nc v ee sdo sdo v ee pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pclkin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 v cc2 v ee 2 rsv2 r set rsv1 nc nc lock v ee3 nc v cc3 reset pin descriptions number symbol type description 1-10 pd9 - pd0 i cmos or ttl compatible parallel da ta inputs. pd0 is the lsb and pd9 is the msb. 11 pclkin i cmos or ttl compati ble parallel clock input. 12 v ee3 - most negative power supply connection for parallel data and clock inputs. 13 v cc3 - most positive power supply connection for parallel data and clock inputs. 14 rsv2 i reserved pin. do not connect. 15, 19, 21, 27, 28, 30, 32, 37 nc i no connect. 16 rsv1 i reserved pin. always connect to v cc . 17 v cc2 - most positive power supply connection fo r internal logic and digital circuits. 18 v ee2 - most negative power supply connection for internal logic and digital circuits. 20 lock o ttl level which is high when the internal pll is locked. 22 r set i external resistor used to set the data output amplitude for sdo and sdo . 23, 26, 29 v ee - most negative power supply connection for shielding (not connected). 24, 25 sdo , sdo o primary, current mode, 75 ? cable driving output (inverse and true) 31 bypass i when high, the smpte scrambler and nrz encoder are bypassed.
14583 - 04 5 of 9 gs7032 33 reset i resets the scrambler when asserted. 34 v cc1 - most positive power supply connection for analog circuits. 35 v ee1 - most negative power supply connection for analog circuits. 36, 38 r vco +, r vco - i differential vco current setting resistor that sets the vco frequency. 39, 43 v ee - most negative power supply connection (substrate). 40 lbwc i ttl level loop bandwidth control that adju sts the pll bandwidth to optimize for lowest jitter. if the pin is set to ground the loop bandwidth is bw min . if the pin is left floating, the loop bandwidth is approximately 3 bw min , if the pin is tied to v cc the loop bandwidth is approximately10 bw min 41, 42 lf+, lf- i differential loop filter pins to opti mize loop transfer performance at low loop bandwidths (nc if not used). 44 sync dis i sync detect disable. logic high disables sync detection. logic low allows 8 bit operation by mapping 000-003 to 000 and 3fc-3ff to 3ff. pin descriptions number symbol type description
14583 - 04 6 of 9 gs7032 typical performance curves (v s = 5v, t a = 25c unless otherwise shown. gu ard band tested to 70c only.) fig. 1 rise/fall times vs. temperature fig. 2 supply current vs. temperature (sdo on) fig. 3a output swing vs. temperature (1000mv) fig. 3b output swing vs. temperature (800mv) fig. 4 waveforms fig. 5 timing diagram 5.25 fall 4.75 rise 5.0 rise 5.0 fall 5.25 rise 4.75 fall 020406080 500 490 480 470 460 450 440 430 420 rise / fall time (ps) temperature (?c) 4.75 5.0 5.25 020406080 155 150 145 140 135 130 125 current (ma) temperature (?c) 4.75 5.0 5.25 020406080 1.01 1.005 1.000 0.995 0.99 output swing (v) temperature (?c) 4.75 5.0 5.25 020406080 0.8075 0.805 0.8025 0.800 0.7975 0.795 0.7925 output swing (v) temperature (?c) t su t hold t clkl = t clkh parallel clock plck 50% parallel data pdn e a v s a v active video 4:2:2 data stream e a v s a v h blnk h blnk sync detect sync detect xxx 3ff 000 000 xxx xxx 3ff 000 000 xxx pclk in pdn
14583 - 04 7 of 9 gs7032 fig. 6 output jitter vs. lbwc fig. 7 output eye diagram (270mb/s) detailed description the gs7032 serializer is a bipolar integrated circuit used to convert parallel data into a serial format according to the smpte 259m-c standard. the device encodes both 8-bit and 10-bit ttl-compatible parallel signals producing serial data rates at 270mb/s. it oper ates from a single 5v supply and is packaged in a 44 pin tqfp. functional blocks within the device include the following: input latches sync detector parallel to serial converter smpte scrambler nrz to nrzi converter internal cable driver pll for 10x parallel clock multiplication lock detect the parallel data (pd0-pd9) and parallel clock (pclkin) are applied via pins 1 through 11 respectively. 1. sync detector the sync detector looks for the reserved words used in the trs-id sync word. the reserved words are 000-003 and 3fc-3ff in 10-bit hexadecimal, or 00 and ff in 8-bit hexadecimal. when the occurrence of either all zeros or all ones at inputs pd2-pd9 are detected, the lower two bits pd0 and pd1 are forced to zeros or ones, respectively. this makes the system compatible with 8-bit or 10-bit data. for non-smpte standard parallel data, the sync detector can be disabled with a logic input, sync detect disable (pin 44). 2. scrambler the scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (x 9 +x 4 +1). this minimizes the dc component in the output serial data stream. the nrz to nrzi converter uses another polynomial (x+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. these functions can be disabled by setting bypass high (pin 31). 3. phase locked loop the pll performs parallel cl ock multiplication and provides the timing signal for the serializer. it is composed of a phase/frequency detector (with no dead zone), charge pump, vco , a divide-by-ten counter, and a divide by two counter. the phase/frequency detector allows a wider capture range and faster lock time than can be achieved with a phase discriminator alone. the discrimination of frequency also eliminates harmonic locking. with this type of discriminator, the pll can be over-dampe d for good stability without sacrificing lock time. the charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. internal voltage clamps are used to constrain the loop filter voltage between approxim ately 1.8 and 3.4 volts. the vco is a differential low phase noise, factory trimmed design that provides increased immunity to pcb noise and precise control of the vco centre frequency. the vco has a pull range of 15% about the centre frequency. the single external resistor, r vco , sets the vco frequency. grounded floating v cc 600 500 400 300 200 100 0 jitter p-p (ps) loop bandwidth control (lbwc) (270mb/s)
14583 - 04 8 of 9 gs7032 4. vco centre frequency selection the recommended r vco value for auto rate smpte 259m-c applications (270mb/s) is 374 ? (see the typical application circuit) . the vco and an internal divider generate the pll clock. 5. lock detect output the lock detect output is available from pin 20 and is high when the loop is locked. when the loop is not locked, the lock detect circuit mutes the serial data outputs. 6. serial outputs the true and complement serial data, sdo and sdo, are available from pins 24 and 25. these outputs will drive two 75 ? co-axial cables with smpte level serial digital video signals. r set calculation: where r load = r pull-up || z o typical application circuit r set 1.154 r load v sdo -------------------------------------- - = 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 gs7032 v ee3 v cc3 rsv2 nc rsv1 v cc2 v ee2 nc lock nc r set sync_dis v ee lf- lf+ lbwc v ee r vco nc r vco+ v ee1 v cc1 reset nc bypass nc v ee nc nc v ee sdo sdo v ee pd9 pd8 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 pclkin v cc j3 j4 v cc v cc v cc v cc v cc 374 100n l r l r 1 1 75 75 100n 54.9 220 j1 lbwc 100n 100n 10k parallel clock input parallel data inputs l = 8.2nh r = 75 ? lock all resistors on ohms, all capacitors in farads, unless otherwise stated. 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 reset v cc
14583 - 04 9 of 9 gennum corporation mailing address: p.o. box 489, stn. a, burlington, ontario, canada l7r 3y3 shipping address: 970 fraser drive, burlington, ontario, canada l7l 5p5 tel. +1 (905) 632-2996 fax. +1 (905) 632-5946 gennum japan corporation shinjuku green tower building 27f, 6-14 -1, nishi shinjuku, shinjuku-ku, tokyo, 160-0023 japan tel. +81 (03) 3349-5501, fax. +81 (03) 3349-5505 gennum uk limited 25 long garden walk, farnham, surrey, england gu9 7hx tel. +44 (0)1252 747 000 fax +44 (0)1252 726 523 gennum corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. the sale of the circuit or device described herein does not imply any patent license, and gennum makes no representation that the circuit or device is free from patent infringement. gennum and the g logo are registered trademarks of gennum corporation. ? copyright 2001 gennum corporation. all rights reserved. printed in canada. www.gennum.com gs7032 package dimensions revision history version ecr date changes and/or modifications 4 136659 may 2005 removed reference to edh fpga core. updated pb-free and rohs compliant part ordering information. 10.00 12.00 10.00 0.80 0.30 12.00 0.20 max radius 0.08 min. radius 0.60 0.15 0.20 min 12? typ 12? typ 1.00 0.10 1.10 0.127 7? max 0? min 0 min pin 1 0.20 min all dimensions in millimetres 44 pin tqfp caution electrostatic sensitive devices do not open packages or handle except at a static-free workstation document identification data sheet the product is in production. gennum reserves the right to make changes at any time to improve reliability, function or design, in order to provide the best product possible.
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